1. Field of the Invention
The present invention relates to a method for chemical-mechanical polishing and, more particularly, to a method for chemical-mechanical polishing to form a thin film.
2. Description of the Related Art
During the fabrication of many semiconductor circuits, the individual devices that make up the circuits are fabricated, in part, by forming a number of layers of material on a wafer and then selectively etching one or more of the layers of material to leave the individual devices. The result of this etch step, however, produces a severe topology with the individual devices forming high points and the etched-away portions forming low points.
FIG. 1 shows a cross-sectional diagram that illustrates a prior-art processed wafer 100 following the etch step that defines the individual devices that make up the circuits on wafer 100. As shown in FIG. 1, wafer 100 has a number of individual devices 110 and a number of etched-away portions 112. In addition, wafer 100 has a top surface 114 with high points defined by the top surfaces of the individual devices 110 and low points defined by the top surfaces of the etched-away portions 112.
One problem with a severe topology is that it is difficult to form a thin, planarized layer of polysilicon on this type of surface. A thin, planarized layer of polysilicon can be used to implement, for example, a local interconnect line. One well-known technique for forming planarized surfaces is known as chemical-mechanical polishing (CMP).
With CMP, an uneven surface is both chemically reacted and mechanically ground to bring down the surface until a substantially flat surface is formed. Conventional CMP processes, however, are subject to dishing, a term that refers to low spots in an otherwise relatively flat surface.
If a layer of polysilicon is deposited on the surface of a processed wafer, such as wafer 100, using conventional deposition techniques, and then planarized using conventional CMP processes, dishing tends to remove a significant amount of polysilicon from the top edges of the individual devices. FIGS. 2A and 2B shows cross-sectional diagrams that illustrate the conventional deposition of polysilicon and subsequent planarization using CMP processes.
As shown in FIG. 2A, conventional deposition techniques have been used to form a layer of polysilicon 210 on the top surface 114 of wafer 100. Conventional CMP planarization requires overdepositing of the material to be planarized by 2×-3× the required final thickness. For example, oxide is typically deposited to a thickness of 12K-18K angstroms to obtain a final thickness of 6.5K angstroms.
Current-generation deposition equipment limits the maximum thickness of the deposited polysilicon to approximately 5K angstroms. (Thicker layers of polysilicon produce film stresses that deform the wafer.) Thus, a final thickness of approximately 2.5K angstroms is the maximum thickness obtainable with current-generation equipment.
Next, as shown in FIG. 2B, polysilicon layer 210 is planarized using chemical-mechanical polishing (CMP) until a thin, substantially-flat layer of polysilicon remains on the surfaces of devices 110. As further shown in FIG. 2B, the CMP process tends to remove more polysilicon at the edges of the top surfaces of devices 110 than at the centers.
This can lead to degraded device performance where the polysilicon has been thinned as shown by arrow A, to an outright open circuit where the polysilicon has been completely removed at the edges as shown by arrow B. Thus, there is a need for a method of forming a thin, planarized layer of polysilicon on the devices which is not subject to polysilicon thinning at the edges of the top surfaces of the devices.